1. Field of the Disclosure
Embodiments of the present disclosure generally relate to multiprocessor devices, and more specifically relates to programmable interrupt routing in a multiprocessor device.
2. Description of the Related Art
Multiprocessor devices containing tens of processing cores and hundreds of peripherals are now commonly implemented to address the high performance requirements of mobile, multi-media and communications infrastructure, automotive safety, and other application segments. These devices may contain myriad serial and parallel connectivity interfaces, and storage interfaces tailored to suit market requirements. Typical hardware architectures of such devices may include multiple processors of various types, e.g., digital signal processors, image processors, graphics processors, and microprocessors, to meet computational needs along with a rich set of peripherals to meet connectivity requirements. Modules included in such devices may include, for example, DMAs (direct-memory-access) accelerators for graphics, vision and video, infrastructural components for interconnect, power management, registers and debug, a memory subsystem, serial peripheral interfaces, high speed video interfaces for display and capture, and a number of support elements for inter-processor communication, timing synchronization, and virtualization components. The complex interaction between the processing elements and the peripherals poses technical challenges in terms of assigning application specific roles for each component. Interrupts and events are one of the basic building blocks for communication between the peripherals and the processors and are typically statically assigned during design which may prohibit some applications.